In semiconductor memory devices, data is read from or written to memory cells in the device according to decoded address information and various other control signals. Such memory devices are used for storage of data and/or program code in personal computer systems, embedded processor-based systems, video image processing circuits, communications devices, and the like. Ferroelectric memories store data in ferroelectric capacitors, and are commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) configurations. In a folded bitline 1T1C architecture, the individual ferroelectric memory cells typically include a ferroelectric (FE) capacitor adapted to store a binary data bit, together with a MOS access transistor, which operates to selectively connect the FE capacitor to one of a pair of complementary bitlines, with the other bitline being connected to a reference voltage for read operations. The individual cells are commonly organized as individual bits of a corresponding data word, where the cells of a given word are accessed concurrently by activation of platelines and wordlines by address decoding control circuitry.
Ferroelectric memory devices provide non-volatile data storage where the cell capacitors are constructed using ferroelectric dielectric material which may be polarized in one direction or another in order to store a binary value. The ferroelectric effect allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within Perovskite crystals in the ferroelectric material. This alignment may be selectively achieved by application of an electric field that exceeds the coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles. The response of the polarization of a ferroelectric capacitor to the applied voltage may be plotted as a hysteresis curve.
Data in a ferroelectric data cell is read by connecting a reference voltage to a first bitline and connecting the cell capacitor between a complementary bitline and a plateline signal. This provides a differential voltage on the bitline pair, which is connected to a differential sense amp circuit. The reference voltage is typically supplied at an intermediate voltage between the voltage associated with a capacitor storing a binary “0” and that of the capacitor storing a binary “1”. The polarity of the sensed differential voltage thus represents the data stored in the cell, which is buffered by the sense amp and provided to a pair of local IO lines. The transfer of data between the ferroelectric memory cell, the sense amp circuit, and the local data bitlines is controlled by various access transistors, typically MOS devices, with switching signals being provided by control circuitry including address decoders and timing circuits in the device.
Connection of the ferroelectric cell capacitor between the plateline pulse and the bitline during a read operation causes an electric field to be applied to the cell capacitor. If the field is applied in a direction to switch or reverse the internal dipoles, more charge will be moved than if the dipoles are not reversed. As a result, the sense amplifier can measure the charge applied to the cell bitlines and produce either a logic “1” or “0” differential voltage at the sense amp terminals. Since reading the cell data is a destructive operation, the sensed data is then restored to the cell following each read operation. To write data to the cell, an electric field is applied to the cell capacitor by a sense amp or write buffer to polarize it to the desired state. Ferroelectric memories provide certain performance advantages over other forms of non-volatile data storage devices, such as flash and EEPROM type memories. For example, ferroelectric memories offer short programming (e.g., write access) times and low power consumption.
Ferroelectric memory devices typically include a number of individually addressable memory cells arranged in an array configuration, wherein the array is typically organized as a matrix of rows and columns. Conventionally, data is stored into a memory array as a row, and read out from the memory array as a row, where the row typically consists of 8, 16, 32, or 64 bits of binary data. During a write operation, row decoder control circuitry provides a plateline pulse signal to the first sides of the ferroelectric cells in a data row, the other sides of which are connected to the array bitlines to receive the data. In a read operation, the decoder provides plateline pulses to the first side of each ferroelectric memory cell in a data row, and sense amplifiers are connected to the other side of the cells to sense a row of stored data bits in parallel fashion. Thus, in a single read operation, an entire row of data bits (e.g., 8, 16, 32, or 64 bits) are obtained from the memory cells in the selected row.
FIG. 1A illustrates a portion of a ferroelectric memory device 2 organized in a folded bitline architecture, having 512 rows (words) and 64 columns (bits) of data storage cells CROW-COLUMN, where each column of cells is accessed via a pair of complementary bitlines BLCOLUMN and BLCOLUMN′. In the first row of the device 2, for example, the cells C1-1 through C1-64 form a 64 bit data word accessible via a wordline WL1 and complementary bitline pairs BL1/BL1′ through BL64/BL64′. The cell data is sensed during data read operations using sense amp circuits 12 (S/A C1 through S/A C64) associated with columns 1 through 64, respectively. In the illustrated configuration, the 1T1C cells CROW-COLUMN individually include a single ferroelectric cell capacitor and an access transistor to connect the cell capacitor between one of the complementary bitlines associated with the cell column and a plateline, where the other bitline is selectively connected to a reference voltage generator 8 or 8′ via one of a pair of switches 8a, 8b, depending upon which word is being accessed for read operations.
In the device 2, cells along WL1 and WL2 (as well as those along WL5, WL6, WL9, WL10, . . . , WL509, WL510) are coupled with bitlines BL1–BL64, whereas cells along WL3 and WL4 (as well as those along WL7, WL8, WL11, WL12, . . . , WL511, WL512) are coupled with bitlines BL1′–BL64′. In reading the first data word along the wordline WL1, the cells C1-1 through C1-64 are connected to the sense amps via the bitlines BL1, BL2 . . . , BL63, and BL64 while the complementary reference bitlines BL1′, BL2′ . . . , BL63′, and BL64′ are connected to the reference voltage generators 8, 8′.
FIGS. 1B and 1C illustrate a single cell 6a (e.g., cell C1-1) in the device 2, which is coupled to bitline BL1, wordline WL1, and plateline PL1, as well as a timing diagram 20 showing waveforms or signals on various nodes during a read operation in the device 2. The 1T1C cell 6a includes a ferroelectric (FE) capacitor CFE1 and a MOS access transistor 10a, where the capacitor CFE1 is coupled between the transistor 10a and a plateline signal PL1, and the transistor 10a is coupled between the capacitor CFE1 and the bitline BL1. Also illustrated is a corresponding sense amp 12 (S/A C1) coupled to the bitline BL1. During a read operation in the device 2, a signal level V1 or V0 is obtained on the array bitline BL1, depending upon the state of the data being read (e.g., binary “1” or “0”, respectively). A reference voltage VREF from the shared reference generators 8, 8′ is ideally between V1 and V0, which is then applied to the complementary bitline BL1′ (e.g., the other input to the sense amp 12).
To read the data stored in the ferroelectric capacitor CFE1, typically the access transistor 10a is turned on by applying a voltage Vwl which is greater or equal to Vdd plus the threshold voltage of the transistor 10a via the wordline WL1 to couple the bitline BL1 to the capacitor CFE1, and the plateline PL1 is thereafter pulsed high, as illustrated in FIG. 1C. This causes charge sharing between the ferroelectric capacitor CFE1 and the bitline BL1 (e.g., bitline BL1 has a non-zero capacitance associated therewith, not shown), whereby the bitline voltage BL1 rises, depending upon the state of the cell data being read. To sense the cell data, the plateline PL1 is returned to 0V and the sense amp 12 is activated (e.g., via a sense amp enable signal SE). One input terminal of the sense amp 12 is coupled to the cell bitline (e.g., data bitline BL1) and the other differential sense amp input is coupled to a reference voltage (e.g., reference bitline BL1′ in this example). In the example of FIGS. 1A–1C, the sense amp 12 is enabled after the plateline signal PL1 is again brought low, a technique referred to as “pulse sensing”. Alternatively, “step sensing” can be used in the device 2, in which the sense amp is enabled via the SE signal while the plateline pulse PL1 is still high.
To optimize the signal level transferred from the capacitor CFE1 to the bitline BL1 in a read operation, the plateline voltage PL1 should be high enough to ensure that the voltage across the capacitor CFE1 is greater than about 90% of the saturation voltage value for the ferroelectric capacitor CFE1. For example, where the saturation value of the capacitor CFE1 is about 1.1 V, the voltage across the capacitor CFE1 should be about 1 V or more during the read operation. If the voltage across capacitor CFE1 is insufficient, the signal level strength at the sense amp 12 is weakened and the signal margin or sensing capability of the sense amp 12 suffers.
As can be seen in FIG. 1C, the bitline voltage BL1 is non-zero once the plateline signal pulse PL1 has been applied to the capacitor CFE1, due to charge from the capacitor CFE1 being transferred to the bitline BL1 and the capacitance thereof. In one example, the bitline voltage BL1 can be of the order of 300–500 mV during the time that PL1 is high. For instance, where the ferroelectric capacitor CFE1 has a saturation voltage of about 1.1 V, the bitline voltage BL1 rises to around 300 mV when reading a “0” data state, and to around 500 mV when reading a “1” data state during the time that PL1 is high. When the plateline PL1 is brought low, the bitline voltage BL1 reduces to around 50 mV for a “0” data state and to around 200 mV for a “1” data” state (e.g., in a range generally between about 25 and 250 mV). In this example, the reference voltage is about halfway between the “0” and “1” states, such as about 125 mV.
Because the voltage across the capacitor CFE1 during the plateline pulse PL1 is the difference between the plateline pulse level PL1 and the bitline voltage on BL1, the plateline pulse signal PL1 itself needs to be much higher than the saturation voltage of the capacitor CFE1, due to the non-zero bitline voltage. In the above example, the plateline pulse on PL1 in the device 2 needs to be about 1.5 V, in order to provide 1 V across the capacitor CFE1 during the read operation. For low power devices, however, the supply level Vdd may not be this high. For example, if the device 2 operates at a supply level Vdd of only 1.3 V, the 1.5 V plateline pulse for PL1 must be generated by a charge pump circuit (not shown) or other voltage boosting circuitry.
Since the saturation voltage of a ferroelectric capacitor is dependent upon the ferroelectric material thereof, redesigning the device 2 for lower threshold ferroelectric capacitors is difficult, involving process integration issues related to processing a different material. Another shortcoming of conventional ferroelectric memories is designing the 1.5 V volt driver circuits for the plateline PL1 using 1.3 V transistors. Moreover, the provision of special high voltages for plateline pulses also increases the device area and cost, and can degrade device reliability. Thus, there is a need for improved ferroelectric memory devices and memory read techniques by which plateline voltage levels can be reduced for a given ferroelectric capacitor material type, without the need for voltage boost circuits.